Shinyoung Park
About Shinyoung Park
Shinyoung Park serves as the Lead MTS Signal Integrity at Rambus, where he has worked since 2021. He holds a Bachelor's, Master's, and PhD in Electrical Engineering from the Korea Advanced Institute of Science and Technology and specializes in signal integrity analysis for DDR5 memory interfaces.
Work at Rambus
Shinyoung Park has been serving as the Lead MTS Signal Integrity at Rambus since 2021. In this role, he is responsible for the design and analysis of various components, including Registered Clock Driver (RCD), Data Buffer (DB), Multiplexed Registered Clock Driver (MRCD), Multiplexed Data Buffer (MDB), and clock driver (CKD). His work focuses on system-level signal and power integrity analysis, particularly for DDR5 memory interface chip development. Prior to his current position, he completed a three-month internship at Rambus in 2019.
Education and Expertise
Shinyoung Park earned his Bachelor's degree in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST) from 2011 to 2015. He continued his studies at KAIST, obtaining a Master's degree in Electrical Engineering from 2015 to 2017. He further advanced his education by completing a Doctor of Philosophy (PhD) in Electrical Engineering at KAIST from 2017 to 2021. His academic background provides a strong foundation for his expertise in signal integrity and power analysis.
Background
Shinyoung Park has a solid educational and professional background in Electrical Engineering. His journey began at the Korea Advanced Institute of Science and Technology, where he completed his undergraduate and graduate studies. After gaining practical experience through an internship at Rambus, he transitioned into a full-time role, where he has been contributing to the field of signal integrity since 2021.
Achievements
In his role at Rambus, Shinyoung Park has been instrumental in the design and analysis of critical components related to memory interface technology. His specialization in system-level signal and power integrity analysis for DDR5 memory interface chip development highlights his contributions to advancing technology in this area. His educational achievements, including a PhD, further underscore his commitment to the field.