Udatha Sambasiva Rao
About Udatha Sambasiva Rao
Udatha Sambasiva Rao is a Lead Engineer at Rambus in Bengaluru, India, where he has worked since 2020. He specializes in the development of GDDR6 memory interface circuits and has extensive experience in advanced semiconductor technologies.
Work at Rambus
Udatha Sambasiva Rao has been serving as a Lead Engineer at Rambus since 2020. In this role, he is primarily focused on the development of GDDR6 memory interface circuits. His tenure at Rambus spans several years, during which he has held multiple positions, including Senior Circuit Design Engineer from 2018 to 2020 and Circuit Design Engineer from 2015 to 2018. His experience at Rambus has allowed him to gain comprehensive knowledge in semiconductor technologies.
Education and Expertise
Udatha Sambasiva Rao holds a Bachelor of Technology (B.Tech.) degree in Electrical, Electronics, and Communications Engineering from R.V.R. & J.C. College of Engineering, which he completed from 2008 to 2012. He further advanced his education by obtaining a Master of Engineering (M.Eng.) in VLSI from the Indian Institute of Science, studying from 2013 to 2015. His educational background supports his extensive expertise in semiconductor technologies and circuit design.
Background
Udatha Sambasiva Rao has built a solid career in the semiconductor industry, particularly in circuit design. He has accumulated significant experience working with advanced semiconductor technologies, including GF 22nm, 14nm, 7nm, and TSMC 45nm, 7nm. His background includes a progressive career at Rambus, where he has developed skills in the entire design process, from schematic design to layout closure.
Achievements
Throughout his career, Udatha Sambasiva Rao has contributed to various projects in the semiconductor field. His involvement in the development of GDDR6 memory interface circuits highlights his role in advancing memory technology. His extensive experience with multiple semiconductor processes demonstrates his capability and commitment to the field.