Venkatesh Bhat
About Venkatesh Bhat
Venkatesh Bhat is a Layout Manager with extensive experience in semiconductor design, currently working at Rambus in Bangalore. He holds a Master of Technology in VLSI and Embedded Systems and has previously held various roles at Sankalp Semiconductor Pvt Ltd, where he led teams in developing high-speed layouts and training programs.
Work at Rambus
Venkatesh Bhat has been working at Rambus as a Layout Manager since 2017. In this role, he is responsible for managing various layout projects in advanced semiconductor technologies. He has led teams in the layout of critical components such as LVDS TX and RX IO libraries in 130nm technology. His leadership extends to overseeing the development of custom IO rings and analog IPs, including LDO, POR, PGD, POK, and BG in 28nm technology. Bhat has also managed layouts for LPDDR2, GPIO IO, and Oscillator across multiple technologies, including 28nm, 45nm, and 65nm.
Education and Expertise
Venkatesh Bhat holds a Master of Technology (MTech) in VLSI and Embedded Systems from B V B College of Engineering & Technology, which he completed from 2006 to 2012. He also earned a Bachelor of Engineering (B.E.) in Electrical, Electronics, and Communications Engineering from the National Institute of Engineering, Mysore, from 2002 to 2006. His foundational education includes completing his SSLC at St. Phylomena Boys High School, Puttur, from 1997 to 2000, and Pre-University studies at Swami Vivekananda Pre University College from 2000 to 2002.
Background
Venkatesh Bhat began his career at Sankalp Semiconductor Pvt Ltd, where he worked for over a decade. He started as an Analog Physical Layout Design Engineer from 2006 to 2017, progressing to Senior Team Lead from 2014 to 2017. During his tenure, he developed a high-speed PHY layout operating at 14GHz in 28nm technology and managed a team of four. He also served as a Training Lead, where he conducted entry-level training for approximately 100 individuals, collaborating with industry experts to design the training syllabus.
Achievements
Throughout his career, Venkatesh Bhat has achieved significant milestones in semiconductor layout design. He has successfully led teams in the layout of various critical components, including the full chip layout of SAR ADC with Analog MUX in 250nm technology. His experience encompasses managing complex projects across multiple technology nodes, demonstrating his expertise in high-speed and analog layout design.