Jeffrey Mc Casland
About Jeffrey Mc Casland
Jeffrey Mc Casland is a Principal Member of Technical Staff at Sandia National Laboratories with extensive experience in FPGA and hardware design.
Current Position at Sandia National Laboratories
Jeffrey McCasland currently holds the position of Principal Member of Technical Staff at Sandia National Laboratories. His extensive experience in hardware and FPGA design contributes to his role in this renowned research and development organization. McCasland has been serving in this capacity since 2003, leveraging his skills in signal processing and system configuration to advance projects within the laboratory.
Previous Role at Intel Corporation
Before joining Sandia National Laboratories, Jeffrey McCasland worked as a Hardware Design Engineer at Intel Corporation. Serving as a contractor from 2001 to 2003 in Chandler, Arizona, McCasland specialized in hardware design, where he gained valuable experience that would later benefit his career in technical staff positions. His work at Intel encompassed various hardware and design projects that contributed to his expertise.
Engineering Experience at Innovasic Semiconductor
Jeffrey McCasland also has a background in engineering at Innovasic Semiconductor. He worked as an Engineer there from 1997 to 1999. During his tenure, McCasland enhanced his skill set in semiconductor technologies, further solidifying his expertise in the electrical engineering field.
Long-Term Tenure at Honeywell Aerospace
From 1987 to 2002, Jeffrey McCasland served as a Principal Engineer at Honeywell Aerospace. Over a span of 15 years, he accumulated vast experience in aerospace engineering, contributing significantly to various projects and technological advancements. His role as a Principal Engineer allowed him to develop a deep understanding of aerospace systems and hardware design.
Educational Background in Electrical Engineering and Signal Processing
Jeffrey McCasland boasts a strong educational foundation in engineering. He earned his MSEE in Signal Processing from The University of New Mexico, where he studied from 1989 to 1991. Prior to that, he completed his BSEE in Electrical Engineering at Iowa State University from 1984 to 1986. This solid academic background laid the groundwork for his successful engineering career.
Expertise in FPGA System Design and Configuration
Jeffrey McCasland has proven expertise in designing space-based FPGA systems using Triple Modular Redundancy (TMR) methodology. He is proficient in configuring FPGA hardware with the Xilinx FPGA configuration manager and has worked extensively with various FPGA platforms including Xilinx, Altera, and Actel. Additionally, McCasland is skilled in utilizing ARM technology in processor-based designs, specifically with TI OMAP processors, and has practical experience in hardware design projects involving DDR3 memory.