Mitesh Devani
About Mitesh Devani
Mitesh Devani is a Technical Lead at STL - Sterlite Technologies Limited, specializing in orchestration modules for 5G core and access components. He has a background in software development and holds a Bachelor of Engineering in Electronics and Communications Engineering from CHAROTAR UNIVERSITY OF SCIENCE AND TECHNOLOGY.
Work at Sterlite Technologies
Mitesh Devani has been serving as a Technical Lead at Sterlite Technologies Limited (STL) since 2018. In this role, he focuses on various orchestration modules that manage 5G core and access components, including Virtual Network Functions (VNFs) and Cloud Native Functions (CNFs). His responsibilities include achieving auto-scaling and one-view monitoring for multiple edge sites. Devani has also developed a VoWifi lab proof of concept utilizing 4G-Core technology, contributing to STL's advancements in telecommunications.
Previous Work Experience
Prior to his current position at STL, Mitesh Devani worked at several organizations in various roles. He was a Junior Software Developer at Cyberoam from 2013 to 2014 in Ahmedabad, India. He then joined Panamax Inc. as a Software Developer from 2014 to 2016, also in Ahmedabad. Following this, he worked as a Senior Software Developer at Quick Heal from 2016 to 2018 in Pune, India. His diverse experience across these companies has equipped him with a broad skill set in software development and telecommunications.
Education and Expertise
Mitesh Devani earned a Bachelor of Engineering (B.Eng.) in Electronics and Communications Engineering from Charotar University of Science and Technology, completing his studies from 2007 to 2011. His educational background provides a solid foundation for his technical expertise in telecommunications and software development. Devani has hands-on experience with various technologies, including Prometheus, Kafka, ELK stack, Helm charts, and Consul over Kubernetes clusters.
Technical Skills and Projects
Mitesh Devani possesses extensive technical skills, particularly in data plane programming for virtual Broadband Network Gateway (vBNG) using the Intel Barefoot Tofino chip. He has designed and developed an edge analytics system with a fully microservice architecture that integrates with a VNF life cycle manager for a complete closed-loop system. His work includes conducting multiple proofs of concept and explorations focused on data plane optimization for Broadband Network Gateway (BNG).