张志远
About 张志远
张志远 is an ASIC Design and Verification Engineer with extensive experience in the field, currently employed at Synaptics Incorporated in Chengdu, China. He specializes in USB design and verification at the chip level and is involved in FPGA debugging, RISC-V bootloader development, and security verification.
Work at Synaptics
Currently employed at Synaptics Incorporated, 张志远 serves as an ASIC Design and Verification Engineer. He has held this position since 2017, contributing to projects in the field of ASIC design and verification. His responsibilities include leading design and verification efforts specifically for USB at the chip level. He also engages in gate level simulation and timing analysis, which are critical for ensuring the functionality and performance of integrated circuits.
Previous Experience at Conexant
张志远 worked at Conexant as an ASIC Design and Verification Engineer from 2006 to 2017. During his 11 years at the company, he gained extensive experience in ASIC design and verification processes. His role involved various aspects of design and verification, laying a solid foundation for his current work in the industry.
Education and Expertise
张志远 obtained a Master's degree in Signal and Signal Processing from the University of Electronic Science and Technology of China (UESTC) from 2003 to 2006. This academic background provided him with a strong understanding of signal processing techniques, which are essential in his current role as an ASIC Design and Verification Engineer.
Technical Skills and Responsibilities
In his current role, 张志远 is involved in FPGA debugging, which is crucial for validating hardware designs. He also works on RISC-V bootloader and security verification, ensuring that the systems meet security standards. His expertise includes conducting gate level simulation and timing analysis, which are essential for assessing the performance and reliability of ASIC designs.