Arvind Ramakrishnan
About Arvind Ramakrishnan
Arvind Ramakrishnan is a Staff Design Verification Engineer at Synaptics Incorporated, where he has worked since 2017. He has extensive experience in system-verilog and specializes in SOC verification for IoT chipsets.
Current Role at Synaptics
Arvind Ramakrishnan serves as a Staff Design Verification Engineer at Synaptics Incorporated, a position he has held since 2017. In this role, he focuses on design verification processes, contributing to the development and validation of innovative technologies. His work is critical in ensuring the reliability and performance of Synaptics' products, particularly in the context of system-on-chip (SoC) verification for Internet of Things (IoT) chipsets.
Previous Experience at Qualcomm
Before joining Synaptics, Arvind Ramakrishnan worked at Qualcomm as a Senior Hardware Engineer from 2014 to 2017. During his tenure, he was involved in various projects that enhanced his expertise in hardware design and verification. His experience at Qualcomm contributed to his skills in developing robust solutions for complex engineering challenges.
Experience at Marvell Semiconductor
Arvind Ramakrishnan had two separate tenures at Marvell Semiconductor. He initially worked as a Digital IC Design Engineer from 2011 to 2014, where he gained valuable experience in integrated circuit design. He briefly returned in 2014 as a Senior Design Engineer for one month. His roles at Marvell helped him build a strong foundation in semiconductor technologies.
Educational Background
Arvind Ramakrishnan holds a Bachelor of Engineering (B.E.) in Electrical, Electronics and Communications Engineering from SSN Institutions, where he studied from 2003 to 2007. He furthered his education by obtaining a Master of Science (M.S.) in Electrical Engineering from Arizona State University, completing his degree from 2007 to 2009. His academic background provides a solid basis for his professional expertise in engineering.
Technical Skills and Expertise
Arvind Ramakrishnan possesses over six years of experience in SystemVerilog and is proficient in using Mentor Questasim and Questa Autocheck tools. He has developed verification frameworks utilizing UVM methodologies, specifically tailored for custom CPU design projects. His specialization in SoC verification for IoT chipsets highlights his technical capabilities in the field of design verification.