Ian Leighton
About Ian Leighton
Ian Leighton is a Senior Digital Design Engineer with over 10 years of experience in ASIC backend flows and tools. He has a strong background in Place and Route, Static Timing Analysis, and FPGA to ASIC conversions, and has worked for notable companies including Synaptics and Smiths Aerospace.
Current Role at Synaptics
Ian Leighton has been employed at Synaptics as a Senior Digital Design Engineer since 2011. In this role, he focuses on digital design engineering, leveraging his extensive background in ASIC backend flows and tools. His tenure at Synaptics has spanned over 13 years, during which he has contributed to various projects and initiatives within the company.
Previous Experience in ASIC Design
Prior to his current position, Ian Leighton worked at ATR International as a Contract ASIC Design Engineer from 2009 to 2011. He also served as a Senior Design Engineer at Smiths Aerospace for eight years, from 1989 to 1997. His experience in these roles has provided him with a solid foundation in ASIC design and development.
Education and Academic Background
Ian Leighton studied at Bournemouth University, where he earned a Master's degree in VLSI from 1994 to 1996. Additionally, he is currently pursuing a Bachelor's degree in Math, Electronics, and Computing at The Open University, a program he has been enrolled in since 1992. His educational background supports his expertise in digital design and engineering.
Technical Skills and Expertise
Ian Leighton possesses over 10 years of experience in ASIC backend flows and tools. His technical skills include proficiency in Place and Route using Synopsys Astro and ICC tools, Static Timing Analysis with Primetime, and ATPG using TetraMax. He also has experience in Verilog HDL design synthesis with Design Compiler, formal verification with Cadence LEC, and physical verification using Hercules and Calibre tools.
Project Experience and Achievements
Throughout his career, Ian Leighton has completed over 30 successful FPGA to ASIC conversions. He has also accumulated 9 years of Place and Route experience, which has enhanced his capabilities in digital design engineering. His work in Static Timing Analysis and ATPG further demonstrates his proficiency in the field.