Jie Liu
About Jie Liu
Jie Liu is a Senior Design Verification Engineer at Synaptics Incorporated, specializing in constrained random-based functional verification using SystemVerilog with UVM. With a strong background in ASIC design and verification, he has over a decade of experience in the field.
Work at Synaptics
Jie Liu has been employed at Synaptics Incorporated as a Senior Design Verification Engineer since 2019. In this role, Liu focuses on functional verification, utilizing constrained random-based methodologies with SystemVerilog and UVM. The position is based in San Jose, California, where Liu contributes to the development and validation of advanced semiconductor technologies.
Previous Experience in ASIC Design and Verification
Before joining Synaptics, Jie Liu worked at Shanghai Fudan Microelectronics Group Co., Ltd as an ASIC Design and Verification Engineer from 2013 to 2019. This six-year tenure in Shanghai, China, involved responsibilities related to ASIC design and verification processes, enhancing Liu's expertise in the field. Additionally, Liu interned at AMD as an ASIC Engineer Intern for seven months in 2012, further building foundational skills in ASIC engineering.
Education and Expertise
Jie Liu holds a Master's degree in Electrical, Electronics and Communications Engineering from Shanghai University, where studies were completed from 2010 to 2013. Liu also earned a Bachelor's degree in the same field from the same institution, graduating in 2010. This educational background provides a solid foundation in electrical engineering principles, which is applied in Liu's professional work.
Technical Skills and Knowledge
Jie Liu possesses strong technical skills in constrained random-based functional verification, particularly using SystemVerilog and UVM. Liu has hands-on experience with Perl scripting, which enhances automation and efficiency in verification tasks. Additionally, Liu demonstrates comprehensive knowledge of system architecture, including AMBA protocols (APB/AHB) and serial communication protocols such as SPI and I2C. This expertise supports effective design verification and problem-solving in ASIC debugging.
Documentation and Communication Skills
In the role of Senior Design Verification Engineer, Jie Liu is experienced in writing specifications and technical documentation. This skill ensures clear communication of design requirements among team members and stakeholders. Liu's ability to articulate complex technical concepts contributes to successful project outcomes and collaborative efforts in the engineering environment.