Mansoor Rahaman
About Mansoor Rahaman
Mansoor Rahaman is a Senior IC Layout Engineer at Synaptics Incorporated in Bengaluru, India, with over a decade of experience in the field. He specializes in high-speed Analog/Mixed Signal Layout Designs and has worked on various critical analog blocks throughout his career.
Work at Synaptics
Mansoor Rahaman has been employed at Synaptics Incorporated as a Senior IC Layout Engineer since 2020. He works in Bengaluru, Karnataka, India, where he focuses on high-speed Analog/Mixed Signal Layout Designs. His role involves managing the layout design process for critical analog blocks, including PLL, ADC, and DAC. He has contributed to multiple IP GDS releases and is proficient in creating and releasing LEF files.
Previous Experience
Prior to his current position, Mansoor worked at Synopsys Inc. as a Senior Layout Design Engineer from 2015 to 2020. He also held a position as a Senior Layout Engineer at IMMS GmbH for one month in 2020. Earlier in his career, he served as a Layout Trainee at SiCon Design Technologies Pvt. Ltd. for nine months in 2014. His diverse experience spans various roles in the semiconductor industry.
Education and Expertise
Mansoor Rahaman holds a Master of Technology (MTech) degree from KL University, which he completed from 2012 to 2014. He also earned a Bachelor's Degree in Electronics and Communications Engineering from Jawaharlal Nehru Technological University from 2007 to 2010. Additionally, he obtained a Diploma in Electronics and Communications Engineering from AANM & VVRSR Polytechnic from 2004 to 2007. His educational background supports his expertise in IC layout engineering.
Technical Skills
Mansoor possesses extensive knowledge in various technical areas relevant to IC layout design. He is skilled in using Cadence Virtuoso and Synopsys Custom Compiler for layout design, along with verification tools such as Mentor Graphics Calibre and Cadence PVS. His proficiency includes handling high-speed layouts, ESD, Electron Migration, and DFM. He has experience with half-cell structured layouts to ensure device matching and shielding of critical signals.
Project Involvement
Throughout his career, Mansoor has worked on significant projects involving top-level IPs such as CM_AFE, APLL_AFE, and LCPLL_AFE. He has managed the entire process from floor-planning to final verification and release. His involvement in these projects highlights his capability in overseeing complex layout designs and collaborating with failure analysis teams to address issues related to chip performance.