Paweł Kasperski
About Paweł Kasperski
Paweł Kasperski is a Principal IC Verification Engineer at Synaptics Incorporated, where he has worked since 2020. He has a strong educational background in electronics and telecommunications, holding a Master's degree from Silesian University of Technology and having studied at Friedrich-Alexander-Universität Erlangen-Nürnberg.
Work at Synaptics
Paweł Kasperski has been employed at Synaptics Incorporated since 2020, serving as a Principal IC Verification Engineer. His role involves overseeing the verification processes for integrated circuits, ensuring that designs meet specified requirements and performance standards. He operates from the Katowice Metropolitan Area, contributing to the company's advancements in semiconductor technology.
Previous Experience in IC Verification
Prior to his current position, Kasperski worked at DisplayLink as a Principal IC Verification Engineer for seven months in 2020. His responsibilities included validating integrated circuit designs to ensure functionality and reliability. Before DisplayLink, he spent a year at Cadence Design Systems as a Principal Design Engineer from 2018 to 2019, further enhancing his expertise in the field.
Career Development at Cadence Design Systems
Kasperski's tenure at Cadence Design Systems included a five-year period as a Lead Design Engineer from 2013 to 2018. In this capacity, he led design projects and collaborated with cross-functional teams to develop innovative solutions. His experience at Cadence laid a strong foundation for his subsequent roles in integrated circuit verification.
Early Career in Digital IC Design
Kasperski began his career at Evatronix, where he worked as a Digital IC Design Engineer from 2010 to 2013. He was responsible for designing digital integrated circuits, contributing to various projects in the field. His journey in Evatronix started with an internship as a Digital IC Designer from 2008 to 2009, providing him with essential hands-on experience in the industry.
Education and Expertise
Paweł Kasperski holds a Master of Science (M.Sc.) degree in Electronics and Telecommunication from Silesian University of Technology, where he studied from 2003 to 2009. He furthered his education at Friedrich-Alexander-Universität Erlangen-Nürnberg, focusing on Elektrotechnik - Elektronik - Informationstechnik for one year in 2007 to 2008. His academic background supports his extensive expertise in integrated circuit design and verification.