Peter Chu
About Peter Chu
Peter Chu is a Firmware Engineer at Synaptics Incorporated, where he has worked since 2014. He has extensive experience in software and firmware development, having held positions at several notable companies including Sony Electronics, Intel, and NVIDIA.
Work at Synaptics
Peter Chu has been employed at Synaptics Incorporated as a Firmware Engineer since 2014. His role involves the development and enhancement of firmware for various technologies, including touch display systems. Over the course of his tenure, he has contributed to projects that improve the functionality and reliability of embedded systems.
Previous Employment Experience
Before joining Synaptics, Peter Chu held several positions in the technology sector. He worked at Sony Electronics as a Senior Firmware Engineer from 1999 to 2005 and as a Senior Software Engineer for one year in 1998. He also served as a Software Engineer at Intel Corporation from 2009 to 2011 and at NVIDIA as a Video Software Engineer from 2005 to 2008. His experience includes a contract position at Sony Computer Entertainment America from 2012 to 2014 and a role at S3 Incorporated as a DSP Firmware Engineer from 1997 to 1998.
Education and Expertise
Peter Chu holds a Bachelor of Science in Electrical Engineering (BSEE) from National Chiao Tung University and a Master of Science in Electrical Engineering (MSEE) from National Taiwan University. He further advanced his education by earning a PhD in Electrical Engineering from the University of Southern California. His educational background provides a strong foundation for his expertise in firmware and software engineering.
Technical Contributions
Peter Chu has developed significant firmware solutions throughout his career. Notably, he created firmware for force sensing technology, which enhances touch display systems. He also developed a micro bootloader firmware that enables reliable startup processes from external flash in embedded systems. Additionally, he validated an updated System-on-Chip simulator that utilizes hardware block description files for modeling new hardware blocks, facilitating the simulation of micro bootloader firmware.