Ujjaval Vyas
About Ujjaval Vyas
Ujjaval Vyas is a Senior ASIC Design Engineer at Synaptics Incorporated, where he has worked since 2019. He holds a Master's degree in Electrical and Electronics Engineering from San Jose State University and has extensive experience in digital logic design, static timing analysis, and ASIC/SoC design.
Work at Synaptics
Ujjaval Vyas has been employed at Synaptics Incorporated as a Senior ASIC Design Engineer since 2019. In this role, he focuses on ASIC and SoC design, applying his expertise in low power techniques and design for debug. Prior to his current position, he worked as an ASIC Design Intern at Synaptics from 2018 to 2019, where he gained foundational experience in digital logic design and static timing analysis. His tenure at Synaptics has been characterized by a commitment to advancing technology in the semiconductor industry.
Education and Expertise
Ujjaval Vyas holds a Master's degree in Electrical and Electronics Engineering from San Jose State University, where he studied from 2016 to 2018. He also earned a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from Vishwakarma Government Engineering College, completing his studies from 2013 to 2016. Additionally, he obtained a Diploma of Engineering in the same field from Government Polytechnic College, Ahmedabad, from 2010 to 2013. His academic background supports his specialization in ASIC/SoC design and proficiency in various EDA tools.
Professional Background
Before joining Synaptics, Ujjaval Vyas served as a Teaching Associate at San Jose State University from 2017 to 2018. He also gained practical experience as a Technical Intern at Bharat Sanchar Nigam Limited in India from 2014 to 2015. His diverse professional background has equipped him with a solid foundation in both theoretical and practical aspects of electrical engineering, particularly in digital logic design and static timing analysis.
Technical Skills and Knowledge
Ujjaval Vyas possesses extensive technical skills relevant to his field. He is proficient in multiple programming languages, including Verilog HDL, System Verilog, Python, and C++. His expertise extends to digital logic design, static timing analysis, and in-depth knowledge of bus protocols such as NVME, PCIE, AXI, and I2C. He is also familiar with computer architecture concepts, including MIPS architecture and virtual memory, which further enhances his capabilities in ASIC design.