Urmila Kalidindi
About Urmila Kalidindi
Urmila Kalidindi is an Analog Layout Design Engineer with experience at MosChip and Synaptics Incorporated, specializing in advanced technology nodes and various functional block designs. She has a diploma in Electronic and Communications Engineering Technology and possesses strong skills in layout design, debugging, and verification tools.
Work at MosChip
Urmila Kalidindi has been employed at MosChip as an Analog Layout Engineer since 2020. Located in Hyderabad, Telangana, India, she has accumulated four years of experience in this role. Her responsibilities include designing and optimizing analog layouts, contributing to the development of various electronic components.
Work at Synaptics Incorporated
Since 2021, Urmila Kalidindi has served as an Analog Layout Design Engineer at Synaptics Incorporated in Bengaluru, Karnataka, India. With three years of experience in this position, she focuses on the design of analog layouts for advanced technology nodes, enhancing the performance and efficiency of electronic devices.
Education and Expertise
Urmila Kalidindi completed her education at A.A.N.M & V.V.R.S.R Polytechnic College, earning a Diploma in Electronic and Communications Engineering Technology from 2017 to 2020. Earlier, she studied at Vivekananda E.M High School, where she achieved her SSC in 2017. Her educational background supports her expertise in analog layout design.
Technical Skills and Knowledge
Urmila possesses a range of technical skills in analog layout design. She has experience with advanced technology nodes, including TSMC22nm and UMC28nm. Her proficiency includes designing layouts for functional blocks such as Opamps, oscillators, and digital logic blocks. She is skilled in using Cadence Virtuoso Layout tools and verification tools like Assura, PVS, and Calibre.
Layout Design Techniques
Urmila Kalidindi has a solid understanding of various layout design techniques. She is knowledgeable in advanced concepts such as signal flow, matching, shielding, and parasitic management. Additionally, she has strong debugging skills for LVS, DRC, and ESD errors, and is experienced in handling ESDs, clamps, and PADS in layout design.