Yicai Y.
About Yicai Y.
Yicai Y. is a Staff ASIC Design Engineer at Synaptics Incorporated, with a Master's degree in Communication and Information System from Tianjin University. He has extensive experience in ASIC design, having previously worked at Marvell Semiconductor and Trident Microsystems.
Work at Synaptics
Yicai Y. has been employed at Synaptics Incorporated as a Staff ASIC Design Engineer since 2017. His role involves integrating Synopsys IPs into system-on-chip (SoC) designs, including components such as CSI, DPHYRX, DSI, DPHYTX, Kilopass OTP, USB, eMMC, and SDIO. He has also contributed to the integration and implementation of the Image Signal Processor Sub-System, utilizing both internal and external intellectual property (IP). His work at Synaptics reflects a focus on enhancing the functionality and performance of ASIC designs.
Previous Experience at Marvell Semiconductor
Before joining Synaptics, Yicai Y. worked at Marvell Semiconductor as a Senior ASIC Design Engineer from 2012 to 2017 in the United States. During his tenure, he focused on advanced ASIC design projects, contributing to the development and optimization of semiconductor technologies. His experience at Marvell provided him with a strong foundation in ASIC design and engineering practices.
Experience at Trident Microsystems
Yicai Y. served as a Senior Hardware Engineer at Trident Microsystems from 2007 to 2012 in Shanghai City, China. In this position, he was responsible for hardware design and development, which contributed to his expertise in engineering and design processes. His role at Trident Microsystems helped him build a solid background in hardware engineering prior to his subsequent positions.
Education and Expertise
Yicai Y. holds a Master's degree in Communication and Information System from Tianjin University, where he studied from 2005 to 2007. He also earned a Bachelor's degree in Electronic Information Engineering from the same institution, completing his studies from 2001 to 2005. His educational background provides a strong foundation in electronic engineering principles and practices, which he applies in his professional work.
Technical Contributions
Yicai Y. has made significant technical contributions throughout his career. He has configured over 12 Synopsys IPs, generated RTL, and performed various engineering tasks such as synthesis, formal verification, static timing analysis, digital verification simulation, and clock domain crossing analysis. He designed a 141 states Finite State Machine for the IFCP Key Ladder Module and a Kilopass controller for implementing security features. His work includes enhancing memory traffic efficiency and achieving a 0 Cache Miss Rate through innovative design solutions.