Rakesh K
About Rakesh K
Rakesh K is an engineer based in Chennai, Tamil Nadu, India, with expertise in static timing analysis and physical design. He has worked at MulticoreWare Inc and Uhnder India, and has experience in ASIC design flow and signal integrity issues.
Work at Uhnder
Rakesh K has been employed at Uhnder India as an Engineer since 2021. His role involves applying his expertise in Static Timing Analysis and Physical Design to various projects. He has been with the company for three years, contributing to the development and optimization of engineering processes.
Previous Experience at MulticoreWare Inc
Rakesh K initially joined MulticoreWare Inc as a Student Intern in 2020, where he worked for five months in Chennai, Tamil Nadu. Following his internship, he transitioned to a full-time Engineer position in 2021. His work has focused on enhancing engineering solutions and addressing complex design challenges.
Experience at ChipEdge Technologies Pvt Ltd
In 2021, Rakesh K worked at ChipEdge Technologies Pvt Ltd for four months in Bangalore Urban, Karnataka, as a Physical Design Engineer. During this time, he gained practical experience in the physical design aspects of integrated circuits, further developing his technical skills.
Education and Expertise
Rakesh K completed his Bachelor of Technology in Electrical, Electronics, and Communications Engineering at Vellore Institute of Technology from 2017 to 2021. He also studied at Sri Chaitanya Junior College, where he achieved an intermediate level in the MPC stream from 2015 to 2017. His education has provided him with a strong foundation in ASIC design flow and various engineering principles.
Technical Skills and Proficiencies
Rakesh K possesses proficiency in Static Timing Analysis, focusing on Setup and Hold violations, and the effects of clock skew. He has a strong understanding of Physical Design flow, covering Partitioning, Floorplanning, Power planning, Placement, Clock Tree Synthesis, and Routing. Additionally, he is experienced in addressing Signal Integrity issues, such as Crosstalk, using the ICC compiler and has worked with Primetime for timing analysis of latches.