Synopsys
Philip Schmidt
R And D Manager
Hong Jyun Chen
Applications Engineer
Tomasz Stanik
Asic Analog Design Engineer
Sneha Gk
Applications Engineer 1
Pratap Neelashetty
Sr. Asic Design Engineer Ii
Pallavi Srikanth
Senior Information Technology Audit Manager
Kishore Kumar Chinta
R&D Engineer
Wei Hua Han
Application Engineer, Principal
Phuc Ngo
Circuit Design Engineer
Anurag Biswal
Research And Development Engineer 1
Sriram Kumar Jayanthi
Analog And Mixed Signal Design Engineer
Gerardo Leon
Chile Customer Success Group (Ccsg) Director