Synopsys
Avag Avetisov
Analog Design, Sr Engineer
Maksymilian Maka
Silicon Validation Engineering Intern
Vinod Khatri
Accountant
Catalina Vilches
R&D Engineer
Vaibhav Garg
Asic Digital Design Engineer, Sr Ii
Weiye (Jerry) Wu
R&D Engineer
Saloni Vyas
Customer Success Manager
Vaibhav Jain
Staff R&D Engineer
Kazu Toguchi
Sr. Staff Application Engineer Cae
Manoj Badyankal
Senior Software Engineer
Vinnie (Weining) Wu
Silicon Validation Engineer
Sravana S Kuruganti
Team Lead